The present invention relates to a semiconductor device including at least first and second insulated gate transistors integrated on a single substrate and a method for manufacturing the same and, more specifically, to a semiconductor device with a MIS structure such as a DRAM (dynamic random access memory) including both a memory cell section and its peripheral circuit section mounted on one chip and a method for manufacturing the same.
To miniaturize and highly integrate a plurality of insulated gate transistors on a semiconductor substrate is generally useful for achieving high performance of an LSI since the area of devices occupied on the substrate is decreased, the current driving power of the devices is increased, the parasitic capacitance thereof is reduced, and so on. A trial product of a CMOS whose gate length is typically 0.1 .mu.m or less has been already successful at research level, and its high performance has been indeed confirmed.
A serious hindrance to the miniaturization is a short-channel effect in which the absolute value of a threshold voltage drops as the gate length decreases. To prevent this, a so-called scaling rule is proposed, and a transistor is decreased in size according thereto, with the result that the impurity concentration of the substrate has to be increased, or the thickness of an insulation film has to be decreased and so has to be the junction depth of a source/drain region (impurity diffusion layer). In particular, the decrease in the junction depth becomes more important as a solution for suppressing the short-channel effect.
On the other hand, the depth of the impurity diffusion layer need to be great to some extent at a point away from a channel in order to mitigate the parasitic resistance of the insulated gate transistor using the salicide technique. In other words, if silicide is formed on the source/drain region, the junction leakage current between the impurity diffusion layer and substrate becomes large. This large leakage current is prevented by forming an impurity diffusion layer having a considerable depth.
A source/drain extension structure is proposed with a view to suppressing the short-channel effect. In this structure, ion implantation for forming a shallow junction is performed to form a so-called extension region of source/drain. A side-wall (gate side-wall) is formed on the side-wall portion of a gate electrode and then ion implantation is carried out to form an impurity diffusion layer having a sufficiently deep junction except where the gate side-wall is formed. That is, the impurity diffusion layer is formed at a position away from the end portion of the extension region having a shallow junction, by the length of the gate side-wall.
A gate side-wall forming process is employed for obtaining the extension structure. Conventionally, the same gate side-wall length is used for all transistors constituting an LSI. Therefore, particularly in a DRAM including a memory cell section and its peripheral circuit section on one chip, the gate side-wall lengths of a transistor with a small channel width used in the memory section and a transistor with a large channel width used in the peripheral circuit section are not matching each other. This is due to the fact that the design rule of the transistor of the peripheral circuit section is close to an isolation pattern, whereas the memory cell section employs a pattern reduced to the limitation of the lithography technique.
For example, an SAC (self-aligned contact) technique using an etching rate difference of a silicon nitride film to a silicon oxide film provided on the gate side-wall, is generally used when a contact hole is formed in the source/drain region of the memory cell section. If, however, the gate side-wall length is not scaled down in accordance with the design rule (scaling rule), no gate side-wall can be formed in the memory cell section. It is therefore difficult to form a contact hole using the SAC technique and thus impossible to form a memory cell section.
As described above, it is necessary to reduce the gate side-wall length according to the scaling rule in the transistor of the memory cell section. On the other hand, when the gate side-wall length is scaled down, an inconvenience occurs in the transistor of the peripheral circuit section.
As has been described, in particular, when silicide is formed on the impurity diffusion layer of the transistor, the junction depth of the impurity diffusion layer has to be sufficiently large in order to decrease the junction leakage current due to the formation of the silicide. If the gate side-wall length is small, impurities are greatly diffused in the horizontal (lateral) direction under the gate side-wall, which seriously influence on the short-channel effect. Therefore, in order to improve the current drive while suppressing the short-channel effect in the transistor of the peripheral circuit section, the gate side-wall length is greatly increased and the resistance of the impurity diffusion layer has to be considerably small.